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ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 1 mc012-0c 11/16/2001 icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. 8-bits single microcontroller with 16/32/64-kbytes of flash, 256 byte +512 byte ram features ? 80c52 based architecture 256 byte ram internal ram and 512 bytes auxiliary ram available three 16-bit timer/counters full duplex serial channel boolean processor power save mode : 1) idle mode 2) power down mode - waken up from interrupt level trigger mode program memory lock ? lock bits (3) four 8-bit i/o ports, 32 i/o lines memory addressing capability ? 64k program memory and 64k data memory cmos and ttl compatible maximum speed ranges at vcc = 5v is 40 mhz and most instructions execute in 0.3 s packages available: ? 40-pin dip ? 44-pin plcc ? 44-pin pqfp 16k/32k/64k byte flash memory with fast-pulse programming algorithm 36 i/o pins(above 44-pin package only) 8 interrupts vectors (above 44-pin package only) low emi mode general description ic89e54, IC89E58, ic89e64 are members of icsi embedded microcontroller family. the ic89e54/58/64 uses the same powerful instruction set, has the same architecture, and is pin-to-pin compatible with standard 80c51 controller devices. they have ic89e54/58/64 all functions and some enhanced function is included. these enhanced functions include 512 bytes auxiliary memory, 36 i/o pins (44 pin package only), 8 interrupts (44 pin package only) with two- level priority, power off flag, low emi mode, power down mode is waken up from interrupt level trigger mode. figure 1. ic89e54/58/64 pin configuration: 40-pin dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 t2/p1.0 t 2ex/p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 wr/p3.6 rd/p3.7 xtal2 xtal1 vss vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp ale/pro g psen p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 4 .com u datasheet
ic89e54/58/64 2 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 top view figure 2. ic89e54/58/64 pin configuration: 44-pin plcc wr/p3.6 rd/p3.7 xtal2 xtal1 vss p4.0 a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 int3/p4.2 vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp p4.1 ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 rst rxd/p3.0 int2/p4.3 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 index 43 65 2144 18 19 20 21 22 23 24 43 42 41 40 25 26 27 28 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 3 mc012-0c 11/16/2001 figure 3. ic89e54/58/64 pin configuration: 44-pin pqfp/lqfp wr/p3.6 rd/p3.7 xtal2 xtal1 vss p4.0 a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 int3/p4.2 v cc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/vpp p4.1 ale/prog psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 rst rxd/p3.0 int2/p4.3 txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 38 12 13 14 15 16 17 18 37 36 35 34 44 43 42 41 40 39 19 20 21 22 4 .com u datasheet
ic89e54/58/64 4 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 figure 4. ic89e54/58/64 block diagram port 1 port 0 port 2 port 3 p1[7:0] p0[7:0] p2[7:0] p3[7:0] timer 2 uart int0 int1 timer 1 timer 0 ale psen rst ea xtal2 xtal1 p4[3:0] 16k/32k/64k main code flash 512 byte aux ram clock & timing sfr block vss vcc 80c32 cpu core port 4 int 2 int 3 256 byte ram 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 5 mc012-0c 11/16/2001 table 1. detailed pin description symbol pdip plcc pqfp i/o name and function p0.0-p0.7 39-32 43-36 37-30 i/o port 0: port 0 is an open-drain, bi-directional i/o port. port 0 pins that have 1s written to them float and can be used as high- impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pullups when emitting 1s. port 0 also receives the command and code bytes during memory program and verification, and outputs the code bytes during program verification. external pullups are required during program verification. p1.0-p1.7 1-8 2-9 40-44 i/o port 1: port 1 is an 8-bit bi-directional i/o port with internal pullups. port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pullups. port 1 also receives the low-order address byte during memory program and verification. 1240i t2(p1.0) : timer/counter 2 external count input. 2341i t2ex(p1.1): timer/counter 2 trigger input. p2.0-p2.7 21-28 24-31 18-25 i/o port 2: port 2 is an 8-bit bi-directional i/o port with internal pullups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pullups. port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses. in this application, it uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8-bit addresses, port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits from a13 to a8 and some control signals during flash programming and verification. p2.6, p2.7 are the control signals while the chip programs and erases. p2.6 is a program command strobe signal. p2.7 is a data output enable signal. 4 .com u datasheet
ic89e54/58/64 6 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 table 1. detailed pin description ( cont i nued) symbol pdip plcc pqfp i/o name and function p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bi-directional i/o port with internal pullups. port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pullups. port 3 also serves the special features of the ic89e54/58/64, as listed below: 10 11 5 i rxd (p3.0): serial input port. 11 13 7 o txd (p3.1): serial output port. 12 14 8 i int0 int0 int0 int0 int0 (p3.2): external interrupt. serve as a14 during memory program and verification. 13 15 9 i int1 int1 int1 int1 int1 (p3.3): external interrupt. serve as a15 during memory program and verification. 14 16 10 i t0 (p3.4): timer 0 external input. 15 17 11 i t1 (p3.5): timer 1 external input. 16 18 12 o wr wr wr wr wr (p3.6): external data memory write strobe. control signal during memory program, verification and erase. 17 19 13 o rd rd rd rd rd (p3.7): external data memory read strobe. control signal during memory program, verification and erase. p4.0-p4.3 23 17 i/o port 4: in mode 0, port 4 is an 8-bit bi-directional i/o port 34 29 with internal pullups. port 4 pins that have 1s written to them are 1 39 pulled high by the internal pullups and can be used as inputs. 12 6 as inputs, port 4 pins that are externally pulled low will source current because of the internal pullups. in mode 1, 2, 3, port 4 is an address strobe signal which appears with rd or wr signals. 12 6 port 4 also serves the special features, as listed below: 139 int2 int2 int2 int2 int2 (p4.3): external interrupt int3 int3 int3 int3 int3 (p4.2): external interrupt rst 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running resets the device. an internal resistor to vss permits a power-on reset using only an external capacitor. a small internal resistor permits power-on reset using only a capacitor connected to vcc. rst is an input control signal during memory program and verification. xtal 2 18 20 14 o crystal 2: output from the inverting oscillator amplifier. xtal 1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 7 mc012-0c 11/16/2001 symbol pdip plcc pqfp i/o name and function psen 29 32 26 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. psen is an input control signal while memory program and verification. ale/ prog 30 33 27 i/o address latch enable: output pulse for latching the low byte of the address during an address to the external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input ( prog ) during pro- grammable memory programming and erase. ea /v pp 31 35 29 i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to ffffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address grater than 3fffh/7fffh re- specting to ic89c54/58 and the device always executes inter- nal program memory in ic89c64. this is also receives the 12 v programming enable voltage (vpp) during flash programming, when 12 v programming is selected. vss 20 22 16 ground: 0v reference. vcc 40 44 38 i power supply: this is the power supply voltage for operation. table 1. detailed pin description ( cont i nued) operating description the detail description of the ic89e54/58/64 included in this description are: ? memory map and registers ? timer/counters ? serial interface ? interrupt system ? other information ? flash memory memory map and registers program memory and data memory table 2 shows program memory and data memory size versus three products. the ic89e54/58/64 series includes a standard ic80c32 and a 16k/32k/64k flash memory. the ic89e54/58/64 includes ic80c32, a 16k/32k/64k flash and some enhanced functions. the figures 3~5 show ic89e54/58/64 program memory architecture and program memory access status versus ea pin. these enhanced functions are described in later descriptions. the program memory and data memory access ranges are listed table 1. the aux ram status is disable after reset, so movx instructions will access external ram. if set enaram bit, the aux ram will be enabled and movx instructions will access aux ram in 0000h~01ffh, access external ram in 0200h~ffffh. figure 6 shows the external data memory and aux ram accesses relation. 4 .com u datasheet
ic89e54/58/64 8 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 figure 5. ic89e54 flash architecture figure 6. IC89E58 flash architecture table 2. program memory and data memory sizes main flash ram size aux ram size ic89e54 16k bytes : [0h~3fffh] 256 bytes : [ 0-ffh] 512 bytes : [ 0-1ffh] IC89E58 32k bytes : [0h~7fffh] 256 bytes : [ 0-ffh] 512 bytes : [ 0-1ffh] ic89e64 64k bytes : [0h~ffffh] 256 bytes : [ 0-ffh] 512 bytes : [ 0-1ffh] internal range ea = 1 4000h 3fffh 0000h ffffh 0000h ffffh external range external range ea = 0 internal range ea = 1 8000h 7fffh 0000h ffffh 0000h ffffh external range external range ea = 0 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 9 mc012-0c 11/16/2001 figure 7. ic89e64 flash architecture figure 8. ic89e54/58/64 data memory architecture internal range (block 1) ea = 1 f000h efffh 0000h ffffh 0000h ffffh internal range (block 2) external range ea = 0 direct/indirect ram 7fh 00h indirect ram ffh 80h sfr ffh 80h 0000h ffffh external range extram = 0 auxiliary internal ram 01ffh 0000h external ram ffffh 0200h extram = 1 4 .com u datasheet
ic89e54/58/64 10 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 figure 9. ic89e54/58/64 sfrs map and reset value (the gray blocks are non-standard.) b 00000000 acc 00000000 p4[3:0] xxxx1111 psw 00000000 t2con 00000000 xicon 00000000 ip xx000000 ie 0x000000 scon 00000000 tcon 00000000 p0 11111111 p1 11111111 p2 11111111 p3 11111111 sbuf xxxxxxxx tmod 00000000 sp 00000000 dpl 00000000 tl0 00000000 p4cona 00000000 rcap2l 00000000 rcap2h 00000000 p4cconb 00000000 tl1 00000000 dph 00000000 tl2 00000000 p43al 00000000 p42al 00000000 p41al 00000000 th0 00000000 p40al 00000000 th2 00000000 ph43ah 00000000 p42ah 00000000 p41ah 00000000 th1 00000000 p40ah 00000000 p2econ 0000xx00 p2eal 00000000 auxr xxx00000 p2eah 00000000 pcon 0xx00000 f8h f0h e8h e0h d8h d0h c8h c0h b8h b0h a8h a0h 98h 90h 88h 80h ffh f7h efh e7h dfh d7h cfh c7h bfh b7h afh a7h 9fh 97h 8fh 87h these descriptions are added from standard ic80c32. so, more information for sfrs and memory refer to ic80c32. 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 11 mc012-0c 11/16/2001 the timers/counters refer to ic80c32 data sheet. the serial interface refer to ic80c32 data sheet. the interrupt system there are 8 interrupt vectors in 44 pins package and 6 interrupt vectors in 40 pins package. eight interrupt vectors only exist in ic89e54/58/64 series. int2 and int3 are new interrupts that add on standard ic80c32. the interrupt information shows in table 3. the interrupt architecture shows in figure 10. external interrupt 2 and 3 control register is xicon shown in following. two additional external interrupts, int2 and int3 , whose function are similar to those of external interrupt 0 and 1 in the standard 80c32. the functions/status of these interrupts are determined/shown by the bits in the xicon(external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the 80c32. its address is at 0c0h. to set/clear bits in the xicon register, one can use the ?setb (/clr) bit? instruction. table 3. eight interrupt information interrupt source vector address polling sequence enable required interrupt type within priority leve settings edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.2 timer/counter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 (1) 33h 6 xicon.2 xicon.0 external interrupt 3 (1) 3bh 7 (lowest) xicon.6 xicon.3 note: 1. interrupt 2 and interrupt 3 exist in ic89e54/58/64 44 pins package. 4 .com u datasheet
ic89e54/58/64 12 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 xicon(c0h) b7 b6 b5 b4 b3 b2 b1 b0 flag name px3 ex3 ie3 it3 px2 ex2 ie2 it2 bit name description 7 px3 external interrupt 3 priority high if set. 6 ex3 external interrupt 3 enable if set. 5 ie3 if it3=1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced. 4 it3 external interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software. 3 px2 external interrupt 2 priority high if set. 2 ex2 external interrupt 2 enable if set. 1 ie2 if it2=1, ie2 is set/cleared automatically by hardware when interrupt is detected/serviced. 0 it2 external interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software. figure 10. ic89e54/58/64 interrupt architecture int0 tf0 tf1 ri/ti tf2/exf2 int2 int3 ie0 xicon.6 xicon.2 xicon.3 xicon.0 it0 ea ex0 et0 ex1 et1 es et2 ex2 ex3 it3 it2 pt2 ps pt1 px1 pt0 px0 int1 ie1 it1 these descriptions are added from standard 80c32. so, more detailed information for interrupts refer to ic80c52. 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 13 mc012-0c 11/16/2001 operation of power-save mode refer to ic80c32 data sheet. instruction definitions refer to ic80c32 data sheet. enhanced function port 4 port 4, sfr p4 at address d8h, is a 4-bit multipurpose programmable i/o port. each bit can be configured individually by software. the port 4 has four different operation modes. in mode 0, p4.0~p4.3 is a bi-directional i/o port which is same as port 1. p4.2 and p4.3 also serve as external interrupt int3 and int2 if enabled. in mode 1, p4.0~p4.3 are read data strobe signals which are synchronized with beginning of read address signal at specified address. these signals can be used as chip-select signals for external peripherals. in mode 2, p4.0~p4.3 are write data strobe signals which are synchronized with beginning of written address signal at specified address. these signals can be used as chip-select signals for external peripherals. in mode 3, p4.0~p4.3 are write data strobe signals which are synchronized with beginning of read or written address signal at specified address. these signals can be used as chip-select signals for external peripherals. when port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the sfrs p4xah, p4xal, p4cona an p4conb. the registers p4xah and p4xal contain the 16-bit base address of p4.x. the registers p4cona and p4conb contain the control bits to configure the port 4 operating mode. here is an example to program the p4.0 as a write strobe signal at the i/o port address 1234h~1237h and positive polarity, and p4.1~p4.3 are used as general i/o ports. mov p40ah,#12h ;define the base i/o address 1234h for p4.0 as an special function pin. mov p40al,#34h mov p4cona,#00001010b ;define the p4.0 as a write strobe signal pin and the compartor, length is 14. mov p4conb,#00h ;p4.1~p4.3 as general i/o port which are the same as port 1. mov p2econ,#10h ;write the p40sinv=1 to inverse the p4.0 write strobe polarity, default is ;negative. then any instruction movx @dptr,a (with dptr=1234h~1237h) will generate the positive polarity write strobe signal at pin p4.0. and the instruction mov p4,#xx will output the bit 3 to bit 1 of data #xx to pin p4.3~p4.1. the sfrs of port 4 are described in following. figure 11 shows architecture of port 4. port 4 base address registers : reset values are 00000000b. p40ah, p40al(85h, 84h) : the base address register for comparator of p4.0. p40ah contains the high-order byte of address, p40al contains the low-order byte of address. p41ah, p41al(95h, 94h) : the base address register for comparator of p4.1. p41ah contains the high-order byte of address, p41al contains the low-order byte of address. p42ah, p42al(adh, ach) : the base address register for comparator of p4.2. p42ah contains the high-order byte of address, p42al contains the low-order byte of address. p43ah, p43al(b5h , b4h) : the base address register for comparator of p4.3. p43ah contains the high-order byte of address, p43al contains the low-order byte of address. 4 .com u datasheet
ic89e54/58/64 14 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 p4conb (c3h) b7 b6 b5 b4 b3 b2 b1 b0 flag name p43fun1 p43fun0 p43cmp1 p43cmp0 p42fun1 p42fun0 p42cmp1 p42cmp0 bit name description 7,6 p43fun1 =00: mode 0. p4.3 is a general purpose i/o port which is the same as port 1. p43fun0 =01: mode 1. p4.3 is a read strobe signal for chip selecting purpose. the address range depends on the sfrs p43ah, p43al and flags p43cmp1, p43cmp0. =10: mode 2. p4.3 is a write strobe signal for chip selecting purpose. the address range depends on the sfrs p43ah, p43al and flags p43cmp1, p43cmp0. =11: mode 3. p4.3 is a read/write strobe signal for chip selecting purpose. the address range depends on the sfrs p43ah, p43al and flags p43cmp1, p43cmp0. 5.4 p43cmp1 chip-select signals for address comparison. p43cmp0 =00: compare the full address (16 bits length) with the base address register p43ah, p43al. =01: compare the 15 high bits (a15-a1) of address bus with the base address register p43ah, p43al. =10: compare the 14 high bits (a15-a2) of address bus with the base address register p43ah, p43al. =01: compare the 8 high bits (a15-a8) of address bus with the base address register p43ah, p43al. 3,2 p42fun1 the p4.2 function control bits which are the similar definition as p42fun1, p42fun0. p42fun0 1,0 p42cmp1 the p4.2 address comparator length control bits which are the similar definition as p42cmp1, p42cmp0 p42cmp0. p4cona (c2h) b7 b6 b5 b4 b3 b2 b1 b0 flag name p41fun1 p41fun0 p41cmp1 p41cmp0 p40fun1 p40fun0 p40cmp1 p40cmp0 bit name description 7,6 p41fun1 the p4.1 function control bits which are the similar definition as p41fun1, p41fun0. p41fun0 5,4 p41cmp1 the p4.1 address comparator length control bits which are the similar definition as p41cmp1, p41cmp0 p41cmp0. 3,2 p40fun1 the p4.0 function control bits which are the similar definition as p40fun1, p40fun0. p40fun0 1,0 p40cmp1 the p4.0 address comparator length control bits which are the similar definition as p40cmp1, p40cmp0 p40cmp0. 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 15 mc012-0c 11/16/2001 p4(d8h) : b7 b6 b5 b4 b3 b2 b1 b0 flag name - - - - p4.3 p4.2 p4.1 p4.0 bit name description 7-4 - these bits are reserved. 3 p4.3 port 4 data bit that output to pin p4.3 at mode 0. 2 p4.2 port 4 data bit that output to pin p4.2 at mode 0. 1 p4.1 port 4 data bit that output to pin p4.1 at mode 0. 0 p4.0 port 4 data bit that output to pin p4.0 at mode 0. figure 11. ic89e54/58/64 port 4 architecture p4.x p4xal p4xah p4xcmp0 p4xcmp1 address bus write enable read enable p4xfun0 p4xfun1 pin p4.x input signal data output rd_cs wr_cs rd/wr_cs p4xcsinv 4 .com u datasheet
ic89e54/58/64 16 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 p2econ(aeh) b7 b6 b5 b4 b3 b2 b1 b0 flag name p43csinv p42csinv p41csinv p40csinv - - p2cn1 p2cn0 bit name description 7 p43csinv the active polarity of p4.3 when pin p4.3 is defined as read/write strobe signal. =1: p4.3 is active high when pin p4.3 is defined as read/write strobe signal. =0: p4.3 is active low when pin p4.3 is defined as read/write strobe signal. 6 p42csinv the similarity definition as p43sinv. 5 p41csinv the similarity definition as p43sinv. 4 p40csinv the similarity definition as p43sinv. 3,2 - reserve 1,0 p2cn1, =00 : pin p2.7-p2.0 is the standard 8052 port 2. p2cn0 =01 : pins p2.7-p2.0 is input buffer port which the port enable address depends on the content of p2eal and p2eah. =10 : pins p2.7-p2.0 is output-latched port which the port enable address depends on the content of p2eal and p2eah. =11 : undefined. figure 12. ic89e54/58/64 port 2 architecture 74373 74244 port 2 p2eal p2eah port 2 output data bus internal data bus p2cn1 p2cn0 port 2 input data bus read write address bus 16-bit comparator mux demux 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 17 mc012-0c 11/16/2001 auxr(8eh) : reset value is xxx0x000b. b7 b6 b5 b4 b3 b2 b1 b0 flag name - - - enaram - od1 od0 aled bit name description 7-5 - these bits are reserved. 4 enaram 1, enable aux ram. 3 - these bits are reserved. 2-1 od1-od0 select the delay periods of oscillation when waking up from power-down mode. od1 od0 delay period 0 0 2,048 clock cycles (default) 0 1 8,192 clock cycles 1 0 32,768clock cycles 1 1 131,072 clock cycles 0 aled 1, turn off ale output while cpu accesses internal flash memory. p2eah, p2eal : the port enable address registers for port 2 is defined as input buffer like 74244, or an output-latched logic like a 74373. the p2eah contains the high-order byte of address, the p2eal contains the low-order byte of address. figure 12 shows architecture of port 2. the following example shows how to program the port 2 as a output-latched port at address 5678h. mov p2eal,#78h ;high-order byte of address to enable port 2 latch function. mov p2eah,#56h ;low-order byte of address to enable port 2 latch function. mov p2econ,#02h ;configure the port 2 as an output-latched port. mov dptr,#5678h ;move data 5678h to dptr. mov a,#55h movx @dptr,a ;the pins p2.7~p2.0 will output and latch the value 55h. when port 2 is configured as 74244 or 74373 function, the instruction ?mov p2,#xx? will write the data #xx to p2 register only but not output to port pins p2.7~p2.0. power down mode when the pd bit in the pcon register is set, the processor enters the power-down mode. in this mode, all of the clocks are stopped, including the oscillator. to exit from power-down mode is by a hardware reset or external interrupts int0 to int3 when enabled and set to level triggered. to ensure that the oscillator is stable before the cpu restarts, the ic89e54/ 58/64 series provide adjustable internal software delay counter. by the default, the device will experience a delay of 2048 clock cycles while the oscillation is recognized. the period of delay is selected by configuring the auxr register bits od0, od1 and od2. reduce emi emission because of on-chip flash, when a program is running in internal program memory space, the ale will be unused. the transition of ale will cause larger noise and emi effect, so it can be turned off to reduce noise and emi emission if it is useless. turning off the ale signal transition only requires setting the bit 0 of the auxr sfr, which is located at 08eh. when ale is turned off, it will be reactivated when the program accesses external rom/ram data or jumps to execute an external rom code. the ale signal will turn off again after it has been completely accessed or program returns to internal rom code space. the aled bit in the auxr register, when set, disables the ale output. 4 .com u datasheet
ic89e54/58/64 18 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 power control register pcon(87h) : b7 b6 b5 b4 b3 b2 b1 b0 flag name smod - - - gf1 gf0 pd idl bit name description 7 smod double baud rate bit. if timer 1 is used to generate baud rate and smod=1, the baud rate is doubled when the serial port is used in modes 1, 2, or 3. 6-4 - these bits are reserved. 3 gf1 general purpose flag bit. 2 gf0 general purpose flag bit. 1 pd power down bit. setting this bit activates power down operation in the ic89e54/58/64. 0 idl idle mode bit. setting this bit activate idle mode operation in the 89e54/58/64. if 1s are written to pd and idl at the same time, pd takes precedence. 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 19 mc012-0c 11/16/2001 flash memory programming the flash architecture of ic89e54/58/64 is shown in figure 13. ic89e54/58 include block 1 and lock bits block. the signature bytes are fixed value reside in mcu, they are read only. block 2 resides in ic89e64 only. figure 13. the flash architecture of ic89e54/58/64 external host mode the ic89e54/58/64 provide the user with a direct flash memory access that can be used for programming into the flash memory without using the cpu. the direct flash memory access is entered using the external host mode. while the reset input (rst) is continually held active (high), if the psen pin is forced by an input with low state, the device enters the external host mode arming state at this time. the cpu core is stopped from running and all the chip i/o pins are reassigned and become flash memory access and control pins. at this time, the external host should initiate a ?read signature bytes? operation. after the completion of the ?read signature bytes? operation, the device is armed and enters the external host mode. after the device enters into the external host mode, the internal flash memory blocks are accessed through the re- assigned i/o port pins by an external host, such as a printed circuit board tester, a pc controlled development board or an mcu programmer. 3 lock bits flash cell 3x8 bits signature bytes 0030h 0032h dummy address 16k flash ( block 1) 0000h 3fffh 3 lock bits flash cell 3x8 bits signature bytes 0030h 0032h dummy address 32k flash ( block 1) 0000h 7fffh 3 lock bits flash cell 3x8 bits signature bytes 0030h 0032h 60k flash ( block 1) 0000h efffh 4k flash ( block 2) f000h ffffh ic89e54 IC89E58 ic89e64 4 .com u datasheet
ic89e54/58/64 20 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 when the chip is in the external host mode, port 0 pins are assigned to be the parallel data input and output pins. port 1 pins are assigned to be the low order address bus signals for the internal flash memory (a0-a7). the first six bits of port 2 pins (p2[0:5]) are assigned to be the upper order address bus signals for the internal flash memory (a8-a13) along with two of the port 3 pins (p3.2 as a14 and p3.3 as a15). two upper order port 2 pins (p2.6 and p2.7) and two upper order port 3 pins (p3.6 and p3.7) along with rst, psen , prog /ale, ea pins are assigned as the control signal pins. the p3. 4 is assigned to be the ready/busy status signal, which can be used for handshaking with the external host during a flash memory programming operation. the flash memory programming operation (erase, program, verify, etc.) is internally self- timed and can be controlled by an external host asynchronously or synchronously. the insertion of an ?arming? command prior to entering the external host mode by utilizing the ?read signature bytes? operation provides additional protection for inadvertent writes to the internal flash memory cause by a noisy or unstable system environment during the power-up or power unstable conditions. the external host mode uses hardware setup mode, which are decoded from the control signal pins, to facilitate the internal flash memory erase, test and programming process. the external host mode commands are enabled on the falling edge of ale/ prog . the list in table 4 outlines all the setup conditions of normal mode. before entering these written modes must have read 3 signature bytes. programming interface some conditions must be satisfied before entering the programming mode. the conditions are listed in table 4. the interface-controlled signals are matched these conditions, then the ic89e54/58/64 will enter received command mode. the flash command is accepted by the flash command decoder in command received mode. the programming interface is listed in figure 14. figure 14. ic89e52/54/64 external host programming signals vss rst psen ale/prog ea/vpp h l prog pulse 12v/h vcc ic89e54/58/64 10k vcc d7-d0 p0 a7-a0 p3.4 p2.6 p2.7 p3.6 p3.7 ready/busy p2.6 p2.7 p3.6 p3.7 a13-a8 a15-a14 p1 p2.5-2.0 p3.3-3.2 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 21 mc012-0c 11/16/2001 table 4. flash programming mode mode (1) rst psen prog ea p2.6 p2.7 p3.6 p3.7 p0[7:0] p1[7:0] p3[3:2] com p2[5:0] hex (3) read signature byte h l h h l l l l do al ah 0 chip erase h l 12v/h h l l l xxx1 block 1 (2) erase h l 12v/h l h l l xxx2 block 2 (2) erase h l 12v/h l l h l xxx4 program main code h l 12v/h l h h h di al ah e program lock bit 1 h l 12v/h h h h h x x x f program lock bit 2 h l 12v/h h h l l xxx3 program lock bit 3 h l 12v/h h l h l xxx5 verify lock bits h l h h h l l h do[3:1] x x 9 verify main code h l h h l l h h do al ah c 1. to read the signature bytes 30h, 31h, 32h are needed before any written command. to read signature bytes is needed after any new mode changed. this operation provides additional protection for inadvertent writes to the internal flash memory cause by a noisy or unstable system environment during the power-up or unstable power condition. if any unstable power condition has happened while written operation proceeds, to read signature bytes again will re-enable written command. (power-on reset voltage is about 2.7v.) 2. block 1 includes flash address from 0000h to 3fffh in ic89e54, from 0000h to 7fffh in IC89E58, from 0000h to efffh in ic89e64. block 2 includes f000h to ffffh. block 2 is resident in ic89e64 only. 3. ?com hex? presents the combination value of [p3.7, p3.6, p2.7, p2.6]. product identification the ?read signature bytes? command accesses the signature bytes that identify the device as ic89e54/58/64 and the manufacturer code. external programmers primarily use these signature bytes, shown in table 4, in the selection of programming algorithms. the read signature bytes command is selected by the byte code of 00h on p3[7:6] and p2[7: 6]. manufacturer code of icsi is ?d5h? that reside in address 30h of signature. the flash memory sizes of mcu are shown in address 31h, code value 04h respect to 16k main flash memory, code value 08h respect to 32k main flash memory, code value 10h respect to 64k main flash memory. the address 32h value of signature byte respect to written operation vpp value, code value ffh respects to 12v and 55h respects to 5v. table 5. signature bytes information addr 30h addr 31h addr 32h ic89e54 (vpp=12v) d5h 04h ffh ic89e54 (vpp=5v) d5h 04h 05h IC89E58 (vpp=12v) d5h 08h ffh IC89E58 (vpp=5v) d5h 08h 05h ic89e64 (vpp=12v) d5h 10h ffh ic89e64 (vpp=5v) d5h 10h 05h 4 .com u datasheet
ic89e54/58/64 22 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 arming command an arming command must take place before a written mode will be recognized by the ic89e54/58/64. this is to prevent accidental triggering of written operation due to noise or programmer error. the arming command is as follows: a read signature bytes command is issued. this is actually a natural step for the programmer, but will also serve as the arming command. after the above sequence, all other written mode commands are enabled. before the read signature bytes command is received, all other written mode commands received are ignored. the ic89e54/8/64 will exit written mode if power off, so arming command is needed every power on for entering external host command mode. external host mode commands the following is a brief description of the commands. see table 4 for all signal logic assignments for the external host mode commands. the critical timing for all erase and program commands, is self-generated by the flash memory controller on-chip. the high-to-low transition of the prog signal initiates the erase and program commands, which are synchronized internally. all the data in the memory array will be erased to ffh. memory addresses that are to be programmed must be in the erased state prior to programming. selection of the erase command to use, prior to programming the device, will be dependent upon the contents already in the array and the desired programming field block. the ?chip erase? command erases all bytes in both memory blocks of the ic89e54/58/64.this command ignores the ?lock bits? status and will erase the security byte. the ?chip erase? command is selected by the byte code of 01h on p3 [7:6] and p2[7:6]. flash operation status detection (ext. host handshake) the ic89e54/58/64 provide two signals mean for an external host to detect the completion of a flash memory operation, therefore the external host can optimize the system program or erase cycle of the embedded flash memory. the end of a flash memory operation cycle (erase or program) can be detected by monitoring the ready/ busy bit at port 3.4. the following two program commands are for programming new data into the memory array. selection of which program command to use for programming will be dependent upon the desired programming field size. the program commands will not enable if the lock bit 2 or lock bit 3 is enabled on the selected memory block. the ?program main code? command program data into a single byte. ports p0[0:7] are used for data in. the memory location is selected by p1[0:7], p2[0:5], and p3[2:3] (a0-a15). the ?program main code? command is selected by the byte code on p3[6:7] and p2[6:7]. the ?verify main code? command allows the user to verify that the ic89e54/58/64 correctly performed an erase or program command. ports p0[0:7] are used for data out. the memory location is selected by p1[0:7], p2[0:5], and p3[2:3] (a0-a15). these commands will not enable if any lock bit is enabled on the selected memory block. ready/ busy busy busy busy busy the progress of the flash memory programming can be monitored by the ready/ busy output signal. the ready/ busy indicates whether an embedded algorithm in written state machine (wsm) is in progress or complete. the ry/ by status is valid after the falling edge of the programming or erase controlled signal. if the output is low (busy), the device is in an erasing/programming state with an internal verification. if the output is high, the device is ready to read data. if ready/ busy signal doesn?t generate a low pulse or doesn?t return from low to high in an expected time, the programming/erasing action will be failed. 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 23 mc012-0c 11/16/2001 programming a ic89e54/58/64 to program new data into the memory array, supply 5 volts to vdd and rst, and perform the following steps. 1. set rst to high and psen to low. 2. read the ?read signature bytes? command to ensure the correct programming algorithm. 3. raise ea high (either 12v or 5v). 4. verify that the memory blocks for programming are in the erased state, ffh. if they are not erased, then erase them using the chip erase command. (chip erase operation will have a ready/ busy signal output from p3.4, if ready/ busy signal doesn?t return from low to high in 7.2 sec, the chip erase operation will be failed.) 5. set p2.6, p2.7, p3.6, p3.7 to a properly programming combination. 6. select the memory location using the address lines (p1[0:7], p2[0:5], p3[2:3]). 7. present the data in on p0[0:7]. 8. pulse ale/ prog . 9. wait for low to high transition on ready/ busy (p3.4). if ready/ busy is from low to high, this address is programmed completely. if ready/ busy pin don?t return from low to high in 720us while programming one byte, the programming operation will be failed. 10. repeat steps 6~9 until programming is finished. lock bits features the ic89e54/58/64 provide three lock bits to protect the embedded program against software piracy. these three bytes are user programmable. the relation between lock bits status and protection type are listed in table 6. program lock bits protection in normal mode lb1 lb2 lb3 1 u u u no program lock feature enabled. 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and data verification is disabled. (?verify signature byte? and ?verify lock bits are still enabled.) 3 p p u same as 2, also further written operation of the flash is disabled 4 p p p same as 3, also external execution is disabled. table 6. lock bits features special issue there are two conditions must be sure. one is p2.6 and p2.7 can not be low levels when rst pin falling edge. another is p4.3 can not be low level while rst falling edge. one of upper case is generate, the program will not be executing correctly. 4 .com u datasheet
ic89e54/58/64 24 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 operating range (1) range ambient temperature v cc oscillator frequency commercial 0c to +70c +4.5v to +5v 3.5 to 40 mhz note: 1. operating ranges define those limits between which the functionality of the device is guaranteed. absolute maximum ratings parameter rating unit operating temperature under bias 0 to +70 c (1) storage temperature range ?65 to +125 c voltage on any other pin to vss ?2.0 to +7.0 v (2) power dissipation (based on package heat 1.5 w transfer limitations, not device power consumption) note: 1. operating temperature is for commercial products defined by this specification. 2. minimum dc input voltage is ?0.5v. during transitions, inputs may undershoot to ?2. 0v for periods less than 20 ns. maximum dc voltage on output pins is vcc + 0.5v which may overshoot to vcc + 2.0v for periods less than 20 ns. 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 25 mc012-0c 11/16/2001 dc characteristics ( ta = 0c to 70c; vcc = 5v +10% ; vss = 0v ) symbol parameter test conditions min max unit v il input low voltage ?0.5 0.2vcc ? 0.1 v v il 1 input low voltage (xtal1, ea ) ?0.5 0.2vcc ? 0.3 v v ih input high voltage 0.2vcc + 0.9 vcc + 0.5 v (except xtal 1, rst, ea ) v ih 1 input high voltage (xtal 1, ea ) 0.7vcc vcc + 0.5 v v sch + rst positive schmitt-trigger 0.7vcc vcc + 0.5 v threshold voltage v sch ? rst negative schmitt-trigger 0 0.3vcc v threshold voltage v ol (1) output low voltage iol = 100 a ? 0.3 v (ports 1, 2, 3) i ol = 1.6 ma ? 0.45 v i ol = 3.5 ma ? 1.0 v v ol 1 (1) output low voltage i ol = 200 a ? 0.3 v (port 0, ale, psen )i ol = 3.2 ma ? 0.45 v i ol = 7.0 ma ? 1.0 v v oh output high voltage i oh = ?10 a 0.9vcc ? v (ports 1, 2, 3, ale, psen ) vcc = 4.5v ~ 5.5v i ol = ?25 a 0.75vcc ? v i ol = ?60 a 2.4 ? v v oh 1 output high voltage i oh = ?80 a 0.9vcc ? v (port 0, ale, psen ) vcc = 4.5v ~ 5.5v i oh = ?300 a 0.75vcc ? v i oh = ?800 a 2.4 ? v i il logical 0 input current (ports 1, 2, 3) v in = 0.45v ? ?50 a i li input leakage current (port 0) v in = 0.45v or vcc ?10 +10 a i tl logical 1-to-0 transition current v in = 2.0v ? ?650 a (ports 1, 2, 3) r rst rst pulldown resister v in = 0v 50 300 k ? note: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port port 0: 26 ma ports 1, 2, 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink greater than the listed test conditions. 4 .com u datasheet
ic89e54/58/64 26 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 power supply characteristics symbol parameter test conditions min max unit icc power supply current (1) vcc=5.0v active mode 12 mhz ? 20 ma 16 mhz ? 26 ma 20 mhz ? 32 ma 24 mhz ? 38 ma 32 mhz ? 50 ma 40 mhz ? 62 ma idle mode 12 mhz ? 5 ma 16 mhz ? 6 ma 20 mhz ? 7.6 ma 24 mhz ? 9 ma 32 mhz ? 12 ma 40 mhz ? 15 ma power-down mode vcc=5.0v ? 50 a note: 1. the i cc test conditions are shown below. minimum v cc for power down is 2 v. figure 15. active mode figure 16. idle mode figure 17. power mode (v cc =2.0v~6.0v) xtal1 gnd nc rst vcc p0 ea vcc vcc clock signal icc xtal2 vcc xtal1 gnd nc rst vcc p0 ea vcc vcc clock signal icc xtal2 xtal1 gnd nc rst vcc p0 ea vcc vcc icc xtal2 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 27 mc012-0c 11/16/2001 figure 18. clock singal waveform for icc tests in active and idle mode (t clch =t chcl =5 ns) ac characteristics (ta=0cto 70c; vcc=5v r 10%; v ss =0v; c1 for port 0, ale and psen outputs=100pf; c1 for other outputs=80pf) external memory characteristics 24 mhz 40 mhz variable oscillator clock clock (3.5 - 40 mhz) symbol parameter min max min max min max unit 1/t clcl oscillator frequency ? ? ? ? 3.5 40 mhz t lhll ale pulse width 68 ? 35 ? 2t clcl ?15 ? ns t avll address valid to ale low 26 ? 10 ? t clcl ?15 ? ns t llax address hold after ale low 31 ? 15 ? t clcl ?10 ? ns t lliv ale low to valid instr in ? 147 ? 80 ? 4t clcl ?20 ns t llpl ale low to psen low 31 ? 15 ? t clcl ?10 ? ns t plph psen pulse width 110 ? 60 ? 3t clcl ?15 ? ns t pliv psen low to valid instr in ? 105 ? 55 ? 3t clcl ?20 ns t pxix input instr hold after psen 0? 0? 0 ? ns t pxiz input instr float after psen ?37 ?20 ? t clcl ?5 ns t aviv address to valid instr in ? 188 ? 105 ? 5t clcl ?20 ns t plaz psen low to address float ? 10 ? 10 ? 10 ns t rlrh rd pulse width 230 ? 130 ? 6t clcl ?20 ? ns t wlwh wr pulse width 230 ? 130 ? 6t clcl ?20 ? ns t rldv rd low to valid data in ? 157 ? 90 ? 4t clcl ?10 ns t rhdx data hold after rd 0? 0? 0 ? ns t rhdz data float after rd ?78 ?45 ? 2t clcl ?5 ns t lldv ale low to valid data in ? 282 ? 165 ? 7t clcl ?10 ns t avdv address to valid data in ? 323 ? 190 ? 8t clcl ?10 ns t llwl ale low to rd or wr low 105 145 55 95 3t clcl ?20 3t clcl +20 ns t avwl address to rd or wr low 146 ? 80 ? 4t clcl ?20 ? ns t qvwx data valid to wr transition 26 ? 10 ? t clcl ?15 ? ns t whqx data hold after wr 31 ? 15 ? t clcl ?10 ? ns t rlaz rd low to address float ? 0 ? 0 ? 0 ns t whlh rd or wr high to ale high 26 57 10 40 t clcl ?15 t clcl +15 ns 0.45v vcc ? 0.5v t chcx t clcl t clch t clcx t chcl 0.7vcc 0.2vcc ? 0.1 4 .com u datasheet
ic89e54/58/64 28 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 serial port timing: shift register mode 24 mhz 40 mhz variable oscillator clock clock (3.5-40 mhz) symbol parameter min max min max min max unit t xlxl serial port clock cycle time 490 510 290 310 12t clcl ?10 12t clcl +10 ns t qvxh output data setup to 406 ? 240 ? 10t clcl ?10 ? ns clock rising edge t xhqx output data hold after 73 ? 40 ? 2t clcl ?10 ? ns clock rising edge t xhdx input data hold after 0 ? 0 ? 0 ? ns clock rising edge t xhdv clock rising edge to ? 417 ? 250 ? 10t clcl ns input data valid external clock drive characteristics symbol parameter min max unit 1/t clcl oscillator frequency 3.5 40 mhz t chcx high time 10 ? ns t clcx low time 10 ? ns t clch rise time ? 10 ns t chcl fall time ? 10 ns 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 29 mc012-0c 11/16/2001 flash program/erase and verification & test mode characteristics symbol parameter min max unit vpph programming and erase enable voltage 11.5 12.5 v vppl programming and erase enable voltage 4.5 6.0 v ipph programming and erase enable current while vpp=vpph - 2.0 ma ippl programming and erase enable current while vpp=vppl - 1.0 ma twscv power setup to command setup low 10 - ms tcvqv command valid to data output valid - 60 ns tavqv address valid to data output valid - 60 ns tcvpl command valid to prog low 30 - ns tshpl vpp setup to prog low 30 - ns tavpl address setup to prog low 30 - ns tdvpl data setup to prog low 30 - ns tplbl prog low to bus y low 1 10 us tblcx command hold after busy low 30 - ns tblax address hold after busy low 30 - ns tblph busy low to prog high 30 - ns tbldx data hold after busy low 30 - us tblbh busy low to busy high 15 480 us tbhsl vpp hold after busy high 1 - us taxqx output hold after address release 0 - ns tcxqx output hold after command release 0 - ns tblbhe busy time while chip erase - 4.5 sec tblbhe1 busy time while block 1 erase (ic89e54) - 1.2 sec tblbhe2 busy time while block 1 erase (IC89E58) - 2.4 sec tblbhe3 busy time while block 1 erase (ic89e64) - 4.0 sec tblbhe4 busy time while block 2 erase (ic89e64) - 0.7 sec 4 .com u datasheet
ic89e54/58/64 30 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 figure 19. external program memory read cycle figure 20. external data memory read cycle timing waveforms t lhll ale t avll t llpl t plph t pliv t llax t plaz t pxiz t pxix a7-a0 instr in a7-a0 t lliv t aviv psen port 0 port 2 a15-a8 a15-a8 t lldv t avll a7-a0 from ri or dpl instr in a7-a0 from pcl t avwl t avdv psen port 0 port 2 ale rd data in a15-a8 from dph a15-a8 from pch t whlh t llwl t llax t rlaz t rldv t rhdz t rhdx t rlrh 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 31 mc012-0c 11/16/2001 figure 21. external data memory write cycle figure 22. shift register mode timing waveform t avll a7-a0 from ri or dpl instr in a7-a0 from pcl t avwl psen port 0 port 2 ale wr data out a15-a8 from dph a15-a8 from pch t whlh t llwl t llax t qvwx t whqx t wlwh instruction ale clock data out data in t xlxl t xhqx t qvxh t xhdv t xhdx valid valid valid valid valid valid valid valid set ti set ri 78 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 .com u datasheet
ic89e54/58/64 32 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 figure 23. read signature bytes timing(arming command) p3[7:6] p2[7:6] prog vcc t cvqv 00h 30h 31h p3[3:2] p2[5:0] p1[7:0] p0[7-0] vpp t wscv d5h 04h/08h/10h 05h/ffh t avqv t avqv t avqv 32h 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 33 mc012-0c 11/16/2001 figure 24. programming timing p3[7:6] p2[7:6] vpp t cvpl t blcx t plbl t blbh t shpl t bhsl t blax t cqcv t slcv t cxqx 0ch/0dh (2) 0eh (1) p3[3:2] p2[5:0] p1[7:0] prog p0[7-0] p3.4(busy) t avpl t bldx t avqv t axqx valid address (3) valid address (3) t blph t dvpl valid data (4) valid data note: 1. 0eh is for code memory programming . in lock bits programming, 0fh, 03h, 05h respect to lock bit 1, 2, 3. 2. 0ch is for code memory verification and 0dh is for concurrent memory verification. 09h is for lock bits verification. 3. address don?t care while lock bits? programming or verification. 4. data don?t care while lock bits? programming. 4 .com u datasheet
ic89e54/58/64 34 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 figure 25. erasing timing p3[7:6] p2[7:6] vpp t cvpl t blcx t plbl t blbhe t blbhen t shpl t bhsl t cqcv t slcv t cxqx 0ch/0dh (2) 01h/02h/04h (1) p3[3:2] p2[5:0] p1[7:0] prog p0[7-0] p3.4(busy) t avqv t axqx valid address (3) t blph valid data note: 1. 01h/02h/04h are for code chip erase/block 1 erase/block2 erase. 2. 0ch is for code memory verification. 09h is for lock bits verification. 4 .com u datasheet
ic89e54/58/64 i nt egrat ed ci rc u i tsol ut i on i nc. 35 mc012-0c 11/16/2001 figure 26. test mode entering timing figure 27. external clock drive waveform figure 28. ac test point note: 1.ac inputs during testing are driven at vcc-0.5v for logic ?1? and 0.45v for logic ?0?. timing measurements are made at vih min for logic ?1? and max for logic ?0?. t cvsl t phch t slsh 1st stage test mode enable 2rd stage test mode enable 59h 59h 89h 89h p2.6 p0[7-0] 0.45v vcc ? 0.5v t chcx t clcl t clch t clcx t chcl 0.7vcc 0.2vcc ? 0.1 vcc - 0.5v 0.45v 0.2vcc + 0.9v 0.2vcc - 0.1v note: 1. ea, prog, p3.7, p2.7 are high level; p3.6 is lower level. 4 .com u datasheet
ic89e54/58/64 36 i nt egrat ed ci rc u i tsol ut i on i nc. mc012-0c 11/16/2001 ordering information commercial range: 0c to +70c speed order part number package 12 mhz ic89e54/58/64-12pl plcc ic89e54/58/64-12w 600mil dip ic89e54/58/64-12pq pqfp 24 mhz ic89e54/58/64-24pl plcc ic89e54/58/64-24w 600mil dip ic89e54/58/64-24pq pqfp 40 mhz ic89e54/58/64-40pl plcc ic89e54/58/64-40w 600mil dip ic89e54/58/64-40pq pqfp i nt egrat ed ci rc u i tsol ut i on i nc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw 4 .com u datasheet

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